A CMOS imager includes a focal plane array of pixel cells, each cell includes a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for producing a photo-generated charge in a doped region of the substrate. In a CMOS imager, the active elements of a pixel cell, for example a four transistor (4T) pixel, perform the necessary functions of (1) photon to charge conversion; (2) transfer of charge to the floating diffusion region; (3) resetting the floating diffusion region to a known state before the transfer of charge to it; (4) selection of a pixel cell for readout; and (5) output and amplification of a signal representing a reset voltage and a pixel signal voltage based on the photo converted charges. The charge at the floating diffusion region is converted to a pixel or reset output voltage by a source follower output transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524, and U.S. Pat. No. 6,333,205, all assigned to Micron Technology, Inc. The disclosures of each of the forgoing patents are hereby incorporated by reference herein in their entirety.
A schematic diagram of a conventional CMOS four-transistor (4T) pixel cell 10 is illustrated in FIGS. 1A and 1B. FIG. 1A is a top-down view of the cell 10; FIG. 1B is a cross-sectional view of the cell 10 of FIG. 1A, taken along line A-A′. The illustrated cell 10 includes a pinned photodiode 13 as a photosensor. Alternatively, the CMOS cell 10 may include a photogate, photoconductor or other photon-to-charge converting device, in lieu of the pinned photodiode 13, as the initial accumulating area for photo-generated charge. The photodiode 13 includes a p+ surface accumulation layer 5 and an underlying n− accumulation region 14 formed in a p-type semiconductor substrate layer 2.
The pixel cell 10 of FIG. 1 has a transfer gate 7 for transferring photocharges generated in the n− accumulation region 14 to a floating diffusion region 3 (i.e., storage region). The floating diffusion region 3 is further connected to a gate 27 of a source follower transistor. The source follower transistor provides an output signal to a row select access transistor having a gate 37 for selectively gating the output signal to a terminal (not shown). A reset transistor having a gate 17 resets the floating diffusion region 3 to a specified charge level before each charge transfer from the n− region 14 of the photodiode 13.
The illustrated pinned photodiode 13 is formed on a p-type substrate 2. It is also possible, for example, to have a p-type substrate base in an n-type epitaxial layer. The n− accumulation region 14 and p+ accumulation region 5 of the photodiode 13 are spaced between an isolation region 9 and a charge transfer gate 7. The illustrated, conventional pinned photodiode 13 has a p+/n−/p− structure.
Imager pixels, including CMOS imager pixels 10 typically have low signal to noise ratios and narrow dynamic range because of their inability to fully collect, transfer and store the electric charge collected by the photosensitive area of the photosensor. In addition, the pixels are subject to kTC noise, which is a thermal dependent noise generated during the reset of the pixel. The kTC noise refers to the random variation of voltage during the reset of a diffusion area or a storage capacitor.
Because the size of the pixel electrical signal is very small, the signal to noise ratio and dynamic range of the pixel should be as high as possible. In addition, customer demands increasingly call for applications requiring higher dynamic range. The use of additional gates to increase the functional operations of the pixel (e.g., electronic shuttering), however, increases the size of the pixel or reduces the fill factor of the pixel.
One invention that has been suggested for dealing with noise in scaled pixels while providing an electronic shutter is a shutter gate. When a shutter gate is implemented in a pixel design, a storage node is also added such that charges accumulated in a photodiode 13 are transferred through the shutter gate to a storage node. The additional storage node allows the floating diffusion node to be reset and readout prior to charge transfer to the floating diffusion node, thus allowing for correlated double sampling and a reduction of kTC noise. The amount of charge the pixel can store also increases since the gated storage node has a greater charge storage capacity than the photodiode node. An example of a pixel incorporating a shutter gate is U.S. application Ser. No. 10/721,191, assigned to Micron Technology Inc., and incorporated herein by reference.
Additionally, in conventional pixel cells, potential barriers may exist in the path of the photo-generated charge as it is transferred from the photo-conversion device to readout circuitry. Such potential barriers may prevent a portion of the photo-generated charge from reaching the readout circuitry, thereby reducing the charge transfer efficiency of the pixel cell and also reducing the quality of a resultant image. Accordingly, what is needed is a relatively simple method for fabricating a pixel cell with an electrical shutter having good charge transfer characteristics with low charge loss.